Basic Electronics (3110016)

DC load line

• DC load line represents the desirable combinations of the collector current IC and the collector-emitter voltage V_CE.
• It is drawn when no signal is given to the input, and the transistor biased with DC supply.

Bias point of transistor

• It the point on DC Load Line, which represents the DC current ${\mathrm{I}}_{\mathrm{CQ}}$ through transistor and voltage ${\mathrm{V}}_{\mathrm{CEQ}}$ across transistor in quiescent or steady state/DC condition.
• The co-ordinates of Q point are ${\mathrm{I}}_{\mathrm{CQ}}$ and ${\mathrm{V}}_{CEQ}$. $\mathrm{Q} = \left( {\mathrm{I}}_{\mathrm{CQ}} , {\mathrm{V}}_{\mathrm{CEQ}} \right)$
• The position of Q point on DC load line depends on application of transistor. When transistor is used as an amplifier, operating point Q should set at the center of DC load line to avoid distortion in output waveform.