Comparison
|
| Parameter |
RTL |
DTL |
TTL |
I2L |
ECL |
CMOS |
| Basic Gate |
NOR |
NAND |
NAND |
NOR |
NOR/OR |
NOR/NAND |
| Power dissipation in mW per gate |
12 |
8 - 12 |
10 |
6nW - 70µW |
40 - 55 |
1 |
| Fan Out |
5 |
8 |
10 |
Depends on injector current |
25 |
50 |
| Noise Immunity |
Normal |
Good |
Very Good |
Poor |
Poor |
Very Good |
| Propagation delay in nS |
12 |
30 |
10 |
25 - 250 |
2 |
70 |
The DTL circuit shown here consists of three stages:
- an input diode logic stage (D1, D2 and R1)
- an intermediate level shifting stage (R3 and R4)
- an output common-emitter amplifier stage (Q1 and R2).
- If both inputs A and B are high (logic 1; near V+), then the diodes D1 and D2 are reverse biased.
- Resistors R1 and R3 will then supply enough current to turn on Q1 (drive Q1 into saturation) and also supply the current needed by R4.
- There will be a small positive voltage on the base of Q1 (VBE, about 0.3 V for germanium and 0.6 V for silicon).
- The turned on transistor's collector current will then pull the output Q low (logic 0; VCE(sat), usually less than 1 volt).
- If either or both inputs are low, then at least one of the input diodes conducts and pulls the voltage at the anodes to a value less than about 2 volts.
- R3 and R4 then act as a voltage divider that makes Q1's base voltage negative and consequently turns off Q1. Q1's collector current will be essentially zero, so R2 will pull the output voltage Q high (logic 1; near V+).
